Petroleum Engineer Semana Du Schneider Banco Ripley Etisalat Beers Banco Ripley Regional Jobs in Mexico City | 50

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28.07.2024
Cyber Security Incident Management Engineer
Mexico, Mexico - Guadalajara
... Engineer About the team The cyber security engineer will work to maintain corporate wide information security data, infrastructure and process secure, to ensure that AstraZeneca’s information assets are adequately protected in relation to confidentiality, integrity and availability.The role is ...
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1000 ASTRAZENECA S.A DE C.V. Company
31.07.2024
Senior QA Automation Engineer
México, MEX-Distrito Federal-Reforma 26
... Engineer Sr Automation Engineer are experienced professionals that develop software programs in order to test code and applications and have a passion for quality processes. They have in-depth knowledge and subject matter expertise in managing functional testing, automating client application ...
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MEX005 Thomson Reuters MX Servicios S.A. de C.V.
31.07.2024
Senior Cloud Engineer
México, MEX-Distrito Federal-Reforma 26
... Engineer Are you passionate about using cloud technologies, open-source, and love working with and developing the latest technologies in a dynamic environment? Do you have a burning desire to move fast and be bold? Then we want you on our team! We are currently seeking a highly motivated cloud ...
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MEX005 Thomson Reuters MX Servicios S.A. de C.V.
23.07.2024
DevOps Tooling engineer
Mexico, Mexico - Guadalajara
... Engineering Excellence team in RD IT is looking for a technically skilled DevOps Tooling Engineer. You’ll be joining a team whose job it is to boost engineering productivity and developer experience. We work across a large engineering group so orientate our Products and Services to maximise ...
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1000 ASTRAZENECA S.A DE C.V. Company
30.07.2024
VLSI Technical SOC/TOP Level Design and Integration Engineer
India, IND-Bangalore Electronic City - S1
... engineer with 7-10 years of experience in RTL Design /Integration skills He/she should have strong knowledge of following Verilog RTL/System Verilog coding SOC/Top-Level integration flows ( integrating multiple IPs and associated, clock domains ) Synthesis ( DC ) and Timing Concepts (STA) ...
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4123 LSI India Research & Development Private Limited